The fabrication of 3-dimensional high aspect ratio structures in semiconductor wafers has been used extensively in making microelectronic devices. Of particular interest is the fabrication of deep structures with positively tapered profile, as shown in FIG. 1a, where the sidewall taper angle is denoted α. In practice, 3-dimensional silicon structures, such as trenches and vias, with a positive taper angle α of 50-80° are often required in both the front-end applications and back-end applications. For example, in the micro-electro-mechanical systems (MEMS), sloped silicon trenches can be used as micro-fluid channels in biochips and as optical fiber alignment devices in micro-mirrors; and silicon vias with positive tapers are used as ink jet nozzles. In the back-end applications, through-wafer vias with a positive taper are used in chip scale packaging (CSP) applications to make advanced microchips more compact and to enable better electrical performances.
In general, there are two primary requirements when manufacturing positively tapered structures, namely the precisely controlled sidewall profile and the relatively high etch rate. The sidewall profile is of particular concern in many applications. For example, in many applications, etching of sloped vias is often followed by physical vapor deposition (PVD) an/or chemical vapor deposition (CVD) to deposit a diffusion barrier and subsequently a metal seed layer, completely covering all the exposed surfaces. Then, the vias are filled with metallic materials in an electroplating process. Thus, a proper taper angle is crucial to ensure the quality of step coverage of the diffusion barrier layer and the metal seed layer, and subsequently the metal filling in the electroplating step. In this regard, the so-called “cusping” in the top portion of the etched structure is a problem one often encounters. When cusping occurs, the very top portion of the sidewall has an inward curvature, as shown in FIG. 1b. Even small cusping could degrade the step-coverage of the diffusion barrier layer and the metal seed layer and cause void formation in subsequent via filling with metals.
On the other hand, the requirement of a high etch rate comes from the concern over manufacturing throughputs. Trenches and vias are frequently required to have depths well over 100 μm. To ensure manufacturability, the fabrication processes must be capable of high etch rates in order to maintain reasonable throughputs. Another major process requirement in this aspect is the high etch selectivity to the mask materials. With the structure depth requirements, a low selectivity to the etch mask materials could have many adverse implications. For example, a very thick photo resist (PR) mask would be needed if the selectivity is too low, e.g., <10:1, and this could have many undesired complications. Hard masks generally have higher etch selectivity than the PR masks. However, putting down a layer of hard mask material and removing it afterwards are more complicated, when compared with using conventional PR masks.
Traditionally, wet KOH etching is used to etching deep sloped silicon structures. On silicon wafers with a (100) crystalline orientation, etched trenches and vias have a taper angle of 54.7 degrees. However, this technique has severe limitations as the taper angle is fixed. In addition, wet KOH etching requires special mask materials and has complications in chemical waste disposal and in residue contaminations. More importantly, wet KOH etching is often hard to be integrated into the state-of-art semiconductor production lines, which employ numerous processing steps under vacuum.
Over the years, techniques of fabricating sloped 3-dimensional semiconductor structures with plasma dry etching have been developed.
Westerman et al. (F. Clayton, R. J. Westerman, and D. Johnson, 2002 GaAs MANTECH: International Conf. On GaAs Manufacturing Technology, pp. 121-124) disclosed a technique of etching tapered GaAs vias with chlorine-based chemistries. With high radio frequency (RF) bias to promote PR mask recession, GaAs vias are etched at rates exceeding 6 μm/min in a BCl3/Cl2 plasma. However, etching a silicon structure in Cl-based chemistries is known for the slow rate and low etch selectivity to PR masks. In fact it is difficult to achieve etch rates of >1 μm/min when etching Si or Ge materials with a BCl3/Cl2 plasma.
Douglas, in U.S. Pat. No. 4,690,729 described a plasma method for etching deep trenches in silicon substrates with controlled sidewall profile. HCl gas is used as an etchant and silicon oxide is used as etch mask. Under reactive ion etching (RIE) plasma conditions, the oxide mask is sputtered during the course of the silicon etching and re-deposited onto the sidewalls of the etched trenches, providing sidewall protection. The SiOx deposited on the sidewall inhibits etching at the bottom of the trench near the sidewall. As a result, the gradual buildup of SiOx on the sidewall and the progress of silicon etching in the vertical direction produce a positively sloped trench sidewall without “grooving” the bottom of the trench. While this method causes little mask undercut, the etch rate is slow and the achievable depth of the silicon trench is limited.
In recent years, there have been intensive efforts in etching sloped silicon structures with F-containing chemistries. For example, Vogel et al. taught in U.S. Pat. No. 4,324,611 a method for tailoring a reagent gas mixture to achieve a high etch rate, high etch selectivity and low breakdown of PR mask in high-density plasma. The disclosed reagent gas mixture includes a primary etchant gas consisting of carbon-fluoride, and a secondary gas containing hydrogen to control the etch selectivity. A tertiary gas containing helium may be also included to prevent the breakdown of the PR mask. In one embodiment for plasma etching silicon dioxide or silicon nitride overlying silicon, the primary gas is C2F6 and the secondary gas is CHF3. However, such etch processes still cannot produce etch rates exceeding 2-3 μm/min because the heavy deposition component of the process reduces etching efficiency significantly.
In U.S. Pat. No. 5,501,893, Laermer et al. disclosed a method in etching silicon at much higher silicon etch rates using F-containing chemistries. The so-called “Bosch process” employs alternating etching and polymerizing steps. Typically, in an etching step, SF6 gas is used; in a polymerizing step, C4F8 gas is used to facilitate polymeric passivation on all exposed surfaces. In an etching step, RF bias facilitates preferential removal of polymeric passivation on the bottom surface, and SF6 facilitates spontaneous and isotropic etching of silicon. The Bosch processes alternatingly repeats between the etching step and the polymerizing step.
The Bosch processes are advantageous in fabricating anisotropic recess structures with vertical sidewall profiles. However, they are not very successful in fabricating structures with a sidewall taper angle of less than 85 to 88 degrees. In order to achieve a positively tapered profile, the balance between etching and polymerizing needs to shift to the polymeric passivation side. In practice, either a high deposition rate or a less effective etching is needed. This can be accomplished by increasing the flow rate of deposition gas, increasing the deposition step time, and/or reducing the RF bias during the etching step. While such approaches could have limited success in producing a sidewall taper angle of slightly less than 90 degrees, there is an increase in the risk of grass formation in the etched structures together with a lower etching rate.
M. Rattner et al. in U.S. Pat. No. 6,849,554 disclosed a method of etching deep trenches with a positive tapered sidewall angle of less than about 88 degrees. The method employs a series of successive etching steps polymer passivation steps and clean-up steps. Alternatively, in one embodiment, the etching step and the polymer deposition step are carried out simultaneously. The etching steps are carried out at a chamber pressure ranging from about 30 mTorr to about 150 mTorr, to provide a lateral undercut, while at the same time etching vertically downward beneath the mask. When a process employs alternatingly repeating etching steps and deposition steps, both steps are carried out at a chamber pressure ranging from about 30 mTorr to about 150 mTorr. From the examples disclosed in the patent, it is suggested that chamber pressure is the main process control for adjusting taper angles by facilitating more isotropic etching at high chamber pressures. Rattner's method does not address the common cusping problem to which the root cause is the isotropic silicon etching.
R. Nagarajan in U.S. Patent Application 20040178171 disclosed another method of etching positively tapered silicon trenches. Nagarajan's technique employs a repetitive sequence of “passivation (C4F8)-isotropic etching (SF6)-mask recession (O2)”, as shown in FIG. 1c. One of the key requirements for this method is that PR mask must have a sloped edge around the periphery of the mask opening. After the first “passivation-isotropic etching-mask recession” cycle, a portion of silicon trench is etched. Meanwhile, the PR mask is also etched and recessed at its edge, thus the mask opening being enlarged. In the next cycle, a new portion of silicon material is etched away, extending the etching depth. The newly etched portion has a lateral dimension defined by the preceding portion, while the preceding portion is further etched laterally so that the lateral dimension is increased. In the end, a staircase-like configuration is created in the trench sidewall, making the etched trench positively sloped.
Yet, this method has its limitations. Obviously, it cannot be readily applied to cases in which hard oxides masks are used. Also, there exists a relationship among the three parameters, namely the sidewall taper angle α, the mask slope angle θ, and the etch selectivity to mask S, as illustrated in the following Equation (see FIG. 2a):tan α=S·tan θIn order to have a small sidewall taper angle α, the mask slope angle θ needs to be small, which is often hard to achieve by hard baking the PR at high temperatures. If these two angles are fixed, the silicon etch selectivity to mask is also fixed. For example, if one wants to achieve a sidewall taper angle of 60 degrees with a PR mask slope angle of 30 degrees, the silicon etching selectivity needs to be 3:1. In other words, the required PR mask needs to have a thickness over 30 μm if the final etch depth is 100 μm. For deep sloped silicon structures, such limitations could be too severe. In practice, this method is more suitable for applications in which the required sidewall taper angle is not too small, for example 80 degrees (see FIG. 2b), or the slower etch rate and etch selectivity are more acceptable.
Weston et al. (D. Weston, W. J. Dauksher, D. Rhine and T. Smekal, Electrochemical Society Proceedings vol. 2002-17, pp. 227-238) reported a study in which positively tapered Si structures were etched using a SF6/C4F8/O2 gas mixture. The effects of SF6/C4F8 gas ratio, RF bias power and plasma chamber pressure on sidewall smoothness and taper angle were investigated. However, the cusping on the etched structures was persistent. A representative example of cusping using a SF6/C4F8/O2 gas mixture is shown in FIG. 2c. 
C. S. Gormley in U.S. Pat. No. 6,818,564 disclosed that etching tapered Si pores with SF6 gas only. No details on the sidewall profile were revealed, but it is reasonable to believe that the sidewall profile should have more severe cusping than what is shown in FIG. 2c. It is well known that silicon etching in SF6 plasma is highly isotropic.
Based on the limitations of the prior art, there is a need for a method which can be used to etch positively tapered deep silicon structures at high etch rate, high selectivity to etch mask materials with precise sidewall profile control.
Nothing in the prior art provides the benefits attendant with the present invention.
Therefore, it is an object of the present invention to provide an improvement which overcomes the inadequacies of the prior art devices and which is a significant contribution to the advancement to the processing of MEMS.
Another object of the present invention is to provide a method of etching trenches in a substrate comprising placing said substrate on a support member in a vacuum chamber; introducing at least one polymer containing gas into said vacuum chamber; igniting a plasma from said polymer containing gas; depositing a polymer on said substrate using said plasma of said polymer containing gas; introducing an etchant containing gas, a polymer containing gas and a scavenger containing gas into said vacuum chamber; igniting a plasma from said etchant containing gas, said polymer containing gas and said scavenger containing gas; etching said substrate using said plasma of said etchant containing gas, said polymer containing gas and said scavenger containing gas; and alternatingly repeating the deposition step and the etching step until a predetermined trench depth and a predetermined sidewall angle are achieved.
Yet another object of the present invention is to provide a method of etching features in a substrate comprising: placing said substrate on a support member in a vacuum chamber; introducing at least one polymer containing gas into a vacuum chamber; igniting a plasma from said polymer containing gas; depositing a polymer on said substrate using said plasma of said polymer containing gas; introducing an etchant containing gas and a polymer containing gas into said vacuum chamber; igniting a plasma from said etchant containing gas and said polymer containing gas; etching said substrate using said plasma of said etchant containing gas and said polymer containing gas; and alternatingly repeating the deposition step and the etching step until a predetermined trench depth and a predetermined sidewall angle are achieved.
Still yet another object of the present invention is to provide a method of etching features in a substrate comprising: placing said substrate on a support member in a vacuum chamber; introducing at least one polymer containing gas into a vacuum chamber; igniting a plasma from said polymer containing gas; depositing a polymer on said substrate using said plasma of said polymer containing gas, said deposition of said polymer having a process on-time of less than about two seconds; introducing an etchant containing gas into said vacuum chamber; igniting a plasma from said etchant containing gas; etching said substrate using said plasma of said etchant containing gas; and alternatingly repeating the deposition step and the etching step until a predetermined trench depth and a predetermined sidewall angle are achieved.
The foregoing has outlined some of the pertinent objects of the present invention. These objects should be construed to be merely illustrative of some of the more prominent features and applications of the intended invention. Many other beneficial results can be attained by applying the disclosed invention in a different manner or modifying the invention within the scope of the disclosure. Accordingly, other objects and a fuller understanding of the invention may be had by referring to the summary of the invention and the detailed description of the preferred embodiment in addition to the scope of the invention defined by the claims taken in conjunction with the accompanying drawings.